Processing devices, such as central processing units (CPUs) and graphics processing units (GPUs), in computer systems may be powered from different supply voltages. Core processing logic that processes data and generates command signals to an external device in a GPU, may be powered by a first supply voltage, while input/output (I/O) logic that drives the command signals onto I/O pads may be powered by a second supply voltage.
To facilitate the communications between the digital core and the I/O pads/blocks that are using the different power supply, a level shifter circuit is designed and inserted in between the core blocks and the I/O pads/blocks. Current level shifter designs are based on either a PMOS/NMOS cross latch loop, or an inverter cross latch loop. For each of these designs, only one latch loop is used, and acts as an uncontrolled pass through voltage level translator.
An example of a single loop level shifter is illustrated in FIG. 1. The level shifter 10 comprises a PMOS transistor 11 and an NMOS transistor 12, connected in series to power voltage Vdd and ground Vss. A PMOS transistor 13 and NMOS transistor 14 are connected to PMOS transistor 11 and NMOS transistor 13 in a latch form and are connected in series between the power voltage Vdd and ground Vss.
The gate of the PMOS transistor 11 is coupled to a voltage output Vout. The gate of the PMOS 13 is connected to the drain of the NMOS 12. The gate of the NMOS 12 is connected to receive an input signal Vin, and the gate of the NMOS 14 is connected to the input signal Vin by an inverter 15.
When an input voltage is applied to Vin, the NMOS 12 and the PMOS 13 are turned on, and the PMOS 11 and the NMOS 14 are turned off. The output signal Vout is therefore a high voltage signal.
When a 0V signal is the input signal Vin, the NMOS 14 and the PMOS 11 are turned on, and the NMOS 12 and the PMOS 13 are turned off. The output signal Vout is therefore a low voltage signal.
Known designs, such as the one illustrated in FIG. 1, may not have the controllable output latching feature. This feature is important in some situations when a constant output of the level shifter is required regardless of the input of the level shifter. For example, in a core re-power-up sequence, the core may not be in a regular working state during this period of time, and the control signal from the core to the I/O pads/blocks may not be correct and meaningful. Pass through level shifters will simply pass the incorrect control signals direct to the I/O pads/blocks, which may result in a malfunction and unpredictable situation. In this scenario, a level shifter with latched output may be used to maintain the I/O pads/blocks pre-set condition until the core is fully powered up and getting into a normal working state.
Known single loop level shifter that support a controllable output latching feature suffer from the glitch and uncertainty when the shifter restores from the latching state to the normal working state which follows the input. Other drawbacks that known designs may have include larger silicon area, more power, complexity, and relatively more duty cycle distortion.
Accordingly, there exists a need for an improved method and apparatus that overcome the above problems encountered by the current level shifters, including the level shifting function and controllable output latching.